// Wafer Manufacturing

India's first precision wafer producer.

Polished silicon wafers (150mm, 200mm) and SiC wafers (100mm, 150mm) — grown, sliced, and polished in India. Zero import lead time. Complete traceability.

Market Context

India produces zero wafers domestically. Today.

Every silicon and SiC wafer used in Indian semiconductor manufacturing is imported from Japan, Korea, or Germany. SixN Materials changes that — with a domestic wafer line that delivers to Gujarat fabs in 48 hours, not 6 weeks.

🔮

Silicon Wafers

CZ-grown 150mm and 200mm polished prime wafers. DSP and SSP finish. TTV < 3 μm.

⚡

Silicon Carbide (SiC) Wafers

4H-SiC wafers for India's fast-growing power electronics sector. Critical substrate for EV inverters, solar converters, and 5G base stations.

◈

Epitaxial Wafers

Si-on-Si and SiC-on-SiC epitaxial growth to customer specification. Confirmed by FTIR and CV profiling. Epi thickness controlled to ±2% uniformity across the wafer.

Epitaxial Growth in Detail

Why epi layer control matters.

Device performance is determined at the epitaxial layer, not the bulk substrate. Our epi process controls thickness uniformity, doping concentration, and defect density — the three variables that determine whether a device built on our wafers performs to spec.

Thickness Uniformity

Controlled to ±2% across the wafer via precision temperature and gas flow control during growth.

Doping Concentration

In-situ doping with real-time monitoring, verified post-growth via CV profiling.

Defect Density

Basal plane dislocation and micropipe density minimized through substrate preparation and growth parameter control.

Manufacturing Process

From crystal to clean-room-ready substrate.

Crystal Growth

CZ pulling (silicon) or PVT seeded sublimation (SiC), under ultra-pure argon with precise dopant control.

Wire Saw Slicing

Multi-wire saw slicing to target thickness. Wire tension optimised for minimum kerf loss and TTV.

Lapping & CMP Polishing

Double-side lapping and Chemical Mechanical Planarization to surface roughness below 0.15 nm Ra.

Metrology & Packaging

XRD, LLS particle scan, warp/bow/TTV, resistivity mapping, micropipe inspection. Nitrogen-purged FOUP packaging.

Target Customers

Matched to India's anchor fabs.

Micron · Sanand150mm/200mm Si prime wafers

Tata-PSMC · Dholera200mm Si for 28nm logic

CG Power · SanandSiC wafers for compound ICs

HCL–Foxconn · UP200mm Si for OSAT

The global SiC wafer market is projected to exceed $4B by 2029, driven by EV adoption. India's EV programme creates a direct domestic demand signal.

The Economics of Domestic Wafers

Why fabs switch, and why they stay.

⏱️

Qualification Stickiness

Once a fab qualifies a wafer supplier, switching costs are extremely high — re-qualification can take 6–12 months. Early domestic entry means long-term stickiness.

💵

Total Cost of Ownership

Even at comparable unit pricing to imports, eliminating 6–8 week freight cycles reduces the inventory buffer every fab must otherwise carry.

🛡️

Supply Chain Resilience

Export control shifts and shipping disruptions are recurring risks for imported substrates. A domestic second source hedges that risk entirely.

Wafer Reclaim Services

Extending the value of every substrate.

Planned for Phase 2 alongside our core wafer production: reclaim processing for test and monitor wafers, restoring them to a usable specification at a fraction of prime wafer cost. This reduces total wafer consumption cost for fabs running high test-wafer volumes.

Detailed Specifications

Production wafer parameters.

Parameter	Silicon (CZ)	4H-SiC (PVT)
Diameter	150mm, 200mm	100mm, 150mm
Orientation	⟨100⟩, ⟨111⟩	4° off-axis ⟨0001⟩
Resistivity	1–50 Ω·cm	0.015–0.028 Ω·cm (n-type)
TTV	< 3 μm	< 5 μm
Warp / Bow	< 25 μm	< 40 μm
Surface Finish	DSP / SSP CMP	CMP polished, one side
Micropipe Density	N/A	< 1 / cm²

All wafers tested to SEMI M1 (Si) and SEMI M55 (SiC). Custom specifications available on request.

Production Roadmap

Phased capacity build — matched to fab demand.

Phase 1 · 2027

Silicon Wafer Pilot Line — 150mm

CZ puller, wire saw, CMP line, and metrology tools. Target: 5,000 wafers/month.

150mm SiCZ GrowthPrime Grade

Phase 2 · 2028

Scale to 200mm + SiC Pilot

Upgrade to 200mm CZ puller. Add PVT crystal growth for 100mm SiC wafers.

200mm Si100mm SiCPVT Growth

Phase 3 · 2029–2030

Full-Scale 200mm Si + 150mm SiC

Full-capacity 200mm silicon line. Upgrade SiC to 150mm PVT. Epitaxial reactor added.

200mm Si150mm SiCEpi Wafers

Request wafer qualification samples.

Pre-production prime wafers with full metrology reports. One qualification — years of supply. Zero import logistics.